Each new generation of DRAM technology provides a greater storage capacity than the previous generation. In order to provide enough granularity to meet a wide range of memory requirements, many digital designs incorporate multiple generations of DRAMs. The larger memories that rely on the latest generations of DRAMs become cost prohibitive until the price cross-over for the new DRAM takes place. Using multiple DRAMs to emulate the next generation DRAM is usually not feasible due to limitations on board space.
International Business Machines Corporation (hereinafter IBM) currently manufactures stacked DRAMs in a TSOJ-32 pin package as IBM part number 42G9062.
This invention facilitates the emulation of a next generation DRAM by utilizing such a component which includes a plurality of DRAMs having a cumulative memory capacity that is at least equal to the capacity of the DRAM component that is to be emulated. The invention permits the use of a common controller to access the next generation DRAM component as well as the current generation multiple DRAM component so as to facilitate migration to the next generation component when such a migration becomes economically expedient. The invention utilizes additional bits from the controller's address signal that are required to address the next generation DRAM, but are not utilized in addressing any one of the lower density DRAMs in the current generation multiple DRAM component. These additional bits are decoded to direct DRAM control signals such as RAS and CAS or WRITE and Output Enable so as to permit one of the plurality of DRAMs to be accessed. For example, the invention contemplates the steering of DRAM control signals such as RAS and CAS on to output lines from a decoder such that only one of the plurality of DRAMs in the current generation component receives both a RAS and a CAS. Thus, the addressing scheme of the next generation memory is utilized to access a memory location in one of the plurality of current generation DRAMs. The invention teaches the use of a component that has a physical footprint that is compatible with the next generation DRAM component that is being emulated, so as to further provide a means for migration to the next generation DRAM component without necessitating a redesign of the circuit board when the use of this new technology becomes economically expedient.
Recent memory designs have utilized a scheme of interleaving memory control signals between multiple discrete memory components. U.S. Pat. No. 5,228,132 issued Jul. 13, 1993 to Neal, et al. teaches a byte-addressable module for achieving output byte parity without using an individual memory device for each parity bit. This is achieved by interleaving RAS and CAS between several discrete DRAM devices on the module. Likewise, U.S. Pat. No. 5,164,916 issued Nov. 17, 1992 to Wu, et al. describes the implementation of a high density memory module including matrices of multiple discrete memory chips on both sides of a printed wiring board. The implementation teaches limited interleaving of RAS and CAS between groups of these memory chips. Both of these inventions teach interleaving control signals among multiple components rather than a single component as in the present invention, and additionally, both fail to address the problem of emulating next generation memory with a single current generation memory component to conserve card space and provide a simple migration path to the next generation memory component.
Inventions that have utilized stacked components have failed to provide adequate emulation of a next generation component. For example, U.S. Pat. No. 5,371,866 issued on Dec. 6, 1994 to Cady, et al. teaches the use of a stacked DRAM device utilizing a quad RAS decoding scheme wherein address bits from the address bus are used to access the stacked component. The invention requires that the addressing scheme for the current generation DRAMs is utilized, thus failing to emulate a next generation component. Furthermore, since a next generation component would require a new controller, the invention fails to provide a simple migration path to the higher capacity component.